Digital computing power increases as the ability to fabricate more electrical circuits in a smaller area increases. As a result, more data is sent to a single chip as more circuits are placed on a single chip. Additionally, the interconnection of many chips within a single computing system increases computing power. In sum, increasing computing power requires the ability to increase the amount of data processed by a single chip and the ability to interconnect many individual chips. One problem often associated with increasing the amount of data sent to a single chip and interconnecting many chips is that the computing system must be synchronized. That is, the processing of data must not only be coordinated between chips, but even within a single chip having multiple channels for communicating with other chips. This coordination of processing data is generally accomplished through the use of a system clock. Electrical circuits which process data use the system clock to coordinate their functions with other circuits in the computing system. Typically, the system clock is sent to all the chips in a computing system and is distributed to circuits within a single chip. However, variations in path lengths, and in driving and receiving circuits, introduce variations in delay of both data signals and in the distributed clock. These variations result in the clock signal being skewed in time with respect to the data signals. Therefore, some means for adjusting the phase of the received clock or data signal must be implemented to ensure that clock signals for various chips and data inputs are in phase with each other.
Traditionally, phase lock loops (PLLs) have been used to extract and adjust clock signals from data signals encoded with redundancy to allow clock regeneration at the receiver. In this way, no separate system clock need be distributed which results in no varying delays of system clocks. PLLs are desirable for this type of application because of their ability to reject noise. Filtering out noise is important for optimizing phase adjustment in the presence of jitter on the incoming signal. A second order PLL usually consists of a voltage controlled oscillator (VCO), a phase comparator and a low pass filter. The output of the phase comparator is the input to the low pass filter and the low pass filter output is the input to the VCO. A signal generated by the phase comparator adjusts the output frequency of the VCO to match the phase and frequency of the incoming data in order to generate a clock signal. The output of the VCO and the incoming data signal are the inputs to the phase comparator. Prior art designs which implement an analog loop filter use at least one discrete capacitor external to the integrated circuit. The problem with this implementation is that the external capacitor element can be the source of parasitic element and noise problems. Prior art designs which implement a digital loop filter, and so avoid the need for external components, typically do not operate fast enough. This is because the clock speed of the VCO is limited by the digital filter. The prior art has failed to implement a digital filter design which has no external components and which does not limit the clock speed of the PLL.
Digital filters are also useful for retiming mesochronous data. Mesochronous data has a baud rate which exactly matches the frequency of the clock, and has an indeterminate phase relationship to the clock signal. The mesochronous data retiming function is particularly useful when signal interconnections are long and system clock skew is high. Phase recovery is accomplished by adjusting the delay on the input data signal so that it may be retimed by the local clock. The adjustment of delay on all input data signals makes it possible that all circuits can operate with the same phase of the clock signal. Prior art attempts at data recovery have employed the technique of selecting the best of many clock phases to retime the data. Adjusting the clock phase rather than the data phase becomes impractical as the number of input data ports requiring phase recovery increases, since it is desirable to synchronize the processing of each input data bit. Prior art attempts to retime the data have also been very complicated. These complicated circuits consume a large amount of circuit area and power which limits the number of data paths which can be retimed on a single chip, thereby limiting the number of mesochronous interconnections that can be made to a single chip.